Desain Filter Pasif untuk Mereduksi Rugi-Rugi Harmonisa Akibat Variasi Beban pada Laboratorium Komputer dan Jaringan Teknik Elektro Universitas Riau

摘要

This study presents a harmonic filter design to reduce losses due to the load harmonic variations in Computers and Networks Laboratory of Electrical Engineering, University of Riau. Filter design is using ETAP software 7.5. Design passive filter using parameters from measurements made on the electrical panel Laboratory of Computer and Network by using a measuring instrument power quality analyzer KEW 6310. The parameters used are the active power (watts), reactive power (Var), apparent power (VA), and power factor (cos φ). ETAP simulation analysis process is done by modeling the entire charging circuit parameters with the actual condi-tions approach such as power grids, transformers, and cables. Harmonic orders reduced are order 5, order 7 and order 11. Harmonic filter is designed for all tests in order to meet the current THD is allowed IEEE stand-ard 519-1992 by 5%. Eight harmonic filters has been done in this case which three filters for harmonic 5th, three filters for harmonic 7th, and two filters for harmonic order 11th.